1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a borderless contact.
2. Description of the Related Art
As semiconductor device integration continuously increases, device dimensions are necessarily accordingly reduced. Since the size of the semiconductor device is gradually reduced, misalignment easily occurs during the semiconductor manufacturing processes.
FIG. 1 is a schematic, cross-sectional view showing an occurrence of misalignment while forming a contact window. As shown in FIG. 1, a shallow trench isolation (STI) structure 105 is formed in a substrate 100, and then a gate 110 is formed on the substrate 100. Preferably, a cap layer 112 is formed on a top surface of the gate 110. Spacers 130, made of silicon nitride, are formed on sidewalls of the gate and the cap layer 112, and source/drain regions 115 are formed on both sides of the gate 110 in the substrate 100. The detailed description of the processes mentioned above are omitted herein because the processes are well known to those skilled in the art.
A planarized silicon oxide layer 150 is formed on the substrate 100, and then a contact window 160 penetrating through the silicon oxide layer 150 is form by photolithography and etching to expose the source/drain regions 115. The contact window 160 can be used as a bitline contact window or a node contact window.
In the above manufacturing process for forming a contact window, the spacing prepared for forming the contact window 160 is small. Misalignment easily occurs while forming the contact window 160. Since the silicon oxide layer 150 and the shallow trench isolation structure 105 are both made of silicon oxide, a portion of the shallow trench isolation structure 105 is also etched due to misalignment. A recess 165, as illustrated in FIG. 1, is easily formed in the shallow trench isolation structure 105 when misalignment occurs. The recess 165 induces some problems, such as leakage current.
In order to avoid the leakage current mentioned above, a borderless contact technology is developed. The borderless contact for which the conductive line width is substantially the same as the contact window width used in current semiconductor fabrication process. As semiconductors enter the deep sub-micron stage, the device dimensions are gradually decreased to effectively raise the operating speed of the entire integrated circuitry. The borderless contact window process is one of the contact window manufacturing processes developed for the high density semiconductor devices.
FIGS. 2A through 2B are schematic, cross-sectional views of a method for forming a borderless contact window. Referring to FIG. 2A, a shallow trench isolation structure 105 is formed in a substrate 100, and a gate 110 is formed on the substrate 100. A roof layer 120 and spacers 130 are formed above and on the sides of the gate 110 respectively. Source/drain regions 115 are formed in the substrate 100.
A conformal silicon nitride cap layer 140 and a planarized silicon oxide layer 150 are sequentially deposited on the substrate 100. The silicon nitride cap layer 140 serves as a stop layer, and photolithography and etching processes are then conducted to form a borderless contact window 160 in the silicon oxide layer 150 above the source/drain regions 115. The borderless contact window 160 is, for example, a bitline contact window or a node contact window.
Referring to FIG. 2B, the silicon nitride cap layer 140 at the bottom of the borderless contact window 160 is removed by hot phosphoric acid to expose the source/drain regions 115.
In the above manufacturing process of forming a borderless contact window, the spacing prepared for forming the borderless contact window 160 is still small, and the borderless contact window 160 is formed at the interface between the source/drain regions 115 and the shallow trench isolation structure 105. The silicon nitride cap layer 140 can protect the shallow trench isolation structure 105 during the etching process; thus, no recess is formed, and leakage current is avoided.
However, the silicon nitride cap layer 140 formed on the substrate 100 induces stress in other regions of the device. As a result, the reliability of the device is decreased due to the stress.
FIGS. 3A through 3C are schematic, cross-sectional views of another method for forming a borderless contact window. Referring to FIG. 3A, a shallow trench isolation structure 205 is formed in a substrate 200, and then a gate 210 is formed on the substrate 200. Lightly doped source/drain regions 215 are formed on both sides of the gate 210 in the substrate 200. A conformal silicon nitride cap layer 220 is formed on the substrate 200. An ion implantation step 225 is then performed to form heavily doped source/drain regions 230 on both sides of the gate 210 in the substrate 200 while using the gate 210 and the silicon nitride cap layer 220 on sidewalls of the gate 210 as a mask. The lightly doped source/drain regions 215 and the heavily doped source/drain regions 230 constitute source/drain regions 235.
Referring to FIG. 3B, a planarized silicon oxide layer 240 is deposited over the substrate 200. The silicon nitride cap layer 220 serves as a stop layer, and photolithography and etching processes are then conducted to form a contact window 245 such as a bitline contact window or a node contact window in the silicon oxide layer 240 above the source/drain regions 235.
Referring to FIG. 3C, the silicon nitride cap layer 220 at the bottom of the contact window 245 is removed by hot phosphoric acid to expose the source/drain regions 235.
In the above method of forming a borderless contact window, the silicon nitride cap layer 220 serves as a buffer layer while forming the borderless contact window 245; thus, no recess is formed in the shallow trench isolation structure 205 and leakage current is avoided. However, the formation of the silicon nitride cap layer 220 is followed by the ion implantation step 225. It is difficult to perform the ion implantation step 225 because the silicon nitride cap layer 220 is hard; as a result, the device adjustment window is narrow.